Trystan Casey
When designing integrated circuits, electrical engineers must consider the propagation delay in VLSI CMOS design. Propagation delay is the time it takes for the input to reach the output. It is calculated as the time difference between when the transitional input reaches 50% of its final value and when the output reaches 50% of its final value. This is also known as gate delay. There are various methods to calculate delay, including the linear delay model, Elmore delay model, Non-Linear Delay Models (NLDM), and RC delay model. The Elmore delay model, for example, estimates the delay from a source (root) to one of the leaf nodes as the sum of the resistance in the path to the ith node multiplied by the capacitance present at the end of the branch.
| Characteristics | Values |
|---|---|
| Elmore Delay Model | Estimates delay from source to leaf node as sum of resistance in path multiplied by capacitance at branch end |
| Linear Delay Model | Delay depends linearly on the fan-out of the gate |
| Parasitic Delay | Time for a gate to drive its internal capacitance |
| Logical Effort | Measures how bad a gate is at producing output current compared to an inverter |
| Propagation Delay | Time for input to cause a change in output; time difference between input reaching 50% of its final value and output reaching 50% of its final value |
| RC Delay Model | Metric used to calculate signal delay between input and output voltage of input signal |
| Non-Linear Delay Models (NLDM) | Highly accurate model derived from SPICE characterizations that accounts for input transition time, wire capacitance, and pin capacitance |
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What You'll Learn
The Elmore Delay Model
> tpd = R1C1 + (R1 + R2)C2 + ... + (R1 + R2 + ... + Ri)Ci
Where:
- Tpd is the total propagation delay
- Ri is the resistance in the path to the ith node
- Ci is the capacitance at the ith node
While the Elmore Delay Model is useful, it has limitations. It cannot accurately determine the logical effort of a gate, which is crucial when modelling large VLSI systems. To address this, alternative models such as the Fitted Elmore Delay and Improved Elmore Delay have been proposed to minimise parasitic delay without increasing transistor size.
In conclusion, the Elmore Delay Model is a valuable tool for estimating delays in VLSI design due to its simplicity and efficiency. However, it has limitations in modelling large systems, and further improvements have been suggested to enhance its accuracy in specific applications.
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Parasitic delay
In the context of the Elmore Delay Model, the parasitic delay is represented as 5C, which is the time taken to drive the internal capacitance. The Elmore model is considered more accurate than the linear-RC model, as it provides a simplistic delay analysis that does not require time-consuming numerical integration or differential equations. It estimates the delay from a source (root) to a leaf node by multiplying the resistance in the path to the node by the capacitance present at the end of the branch.
The parasitic delay can be calculated as the ratio between the output capacitance of a complex gate and the capacitance of the input of the inverter. The output capacitance is determined by adding the size of the transistors directly connected to the output. In the case of an inverter, to ensure simultaneous output charge and discharge, the size of the PMOS must double due to electron mobility, resulting in an input capacitance of 3.
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Intrinsic delay
The Elmore Delay Model is another method used to estimate intrinsic delay in VLSI design. It calculates the delay from a source (root) to one of the leaf nodes as the sum of the resistance in the path to the ith node multiplied by the capacitance present at the end of the branch. This model provides a simplistic delay analysis that avoids the complexity of numerical integration and differential equations associated with an RC network.
It's important to note that intrinsic delay is largely dependent on the size of the transistors forming the gate. As the size of the transistors increases, so do the internal capacitors, leading to greater intrinsic delay. Therefore, when designing VLSI systems, it is crucial to consider the parameters related to gates, nodes, and timing analysis to ensure optimal performance and meet the required timing specifications.
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Propagation delay
The propagation delay of a logic gate is defined as the time it takes for the effect of change in input to be visible at the output. It is the time required for the input to be propagated to the output. It is normally defined as the difference between the times when the transitioning input reaches 50% of its final value and the time when the output reaches 50% of the final value, showing the effect of the input change. Here, 50% is defined as the logic threshold where the output, or any signal, is assumed to switch its states.
The propagation delay depends on the input transition time (slew rate) and the output load. The output transition time is governed by the same two factors as propagation delay, so for better transition times, both of these should be less. The Elmore Delay Model estimates the delay from a source (root) to one of the leaf nodes as the sum of the resistance in the path to the ith node multiplied by the capacitance present at the end of the branch. It is a simplistic delay analysis that avoids time-consuming numerical integration/differential equations of an RC network.
The Elmore delay is extremely efficient to compute and it gives insight into approximation algorithms. However, it cannot accurately determine the logical effort of a gate, which is important in modelling large VLSI systems. The logical effort measures how bad a gate is at producing output current compared to an inverter. This concept is crucial to analyzing the delay of any standard basic logic gate in combination with a load that can be abstracted as a logic gate module or a functional block.
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Non-Linear Delay Models (NLDM)
The Non-Linear Delay Model (NLDM) is a highly accurate timing model used for static timing analysis (STA) in Very Large Scale Integration (VLSI) systems. It is derived from SPICE (Simulation Program with Integrated Circuit Emphasis) characterisations, which are used to simulate electrical circuits.
NLDM is widely used for the characterisation of standard cells in deep sub-micron technology, where linear delay models are inaccurate. It is a two-dimensional model with input transition time and output load capacitance as its two independent variables. The output transition time is characterised by these two variables, and the output delay is calculated using a lookup table. The NLDM model is represented in table form, with entries denoting the delay.
NLDM is also used for output transition time, which is characterised by input transition time and output load. This separates two-dimensional tables used for computing the output rise and fall transition times of a cell. These are denoted by rise_transition and fall_transition at the output. For example, an input fall transition time of 0.3ns and an output load of 0.16pf will correspond to a rise delay of 0.1018 in an inverter.
NLDM driver models characterise input-to-output delay and output transition times with sensitivity to input transition time, output load, and side input states. However, NLDM only captures three output points, which is insufficient to reflect the non-linearities of circuits at lower geometries (65nm and below) during STA. The classical case of this insufficiency is when driver resistance is significantly less than the impedance of the net it is driving. The NLDM receiver model also fails to capture the Miller effect, which dominates delay calculation for very small impedance nets.
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Frequently asked questions
The Elmore Delay model estimates the delay from a source (root) to one of the leaf nodes as the sum of the resistance in the path to the ith node multiplied by the capacitance present at the end of the branch. It is a simplistic delay analysis that avoids time-consuming numerical integration/differential equations of an RC network.
Parasitic delay is the time for a gate to drive its internal capacitance. It is the constant part of the Elmore Delay model.
Intrinsic delays are the delays internal to the gate, from the input pin of the cell to the output pin of the cell. Extrinsic or wire delays are calculated using output drive strength, input capacitance and wire load models.
Gate delay is calculated using Non-Linear Delay Models (NLDM). NLDM is highly accurate and is derived from SPICE characterizations. The delay is a function of the input transition time, wire capacitance, and pin capacitance of the driven cells.
